Efficient SoC Design with Homogeneous Processor Arrays

It is our opinion that the system-on-chip, all-in-one approach to parallel digital signal processing combining the homogeneous processor array with large amounts of data memory, will be the core of future embedded digital signal processing applications. In this paper we present two radical approaches to efficient system-on-chip (SoC) design with homogeneous processor arrays for real-time applications. We propose two novel techniques to enhance the throughput of the SoC designed systolic arrays. A systolic array control mechanism based on very long instruction word (VLIW) principles is presented and a proposal is given for simultaneous execution of independent algorithm data sets, or even different algorithms, on the programmable systolic array, multithreaded systolic computation. Simulation results of our multithreading approach are based on a set of linear algebra algorithms.